September 2013, In a recent telephone briefing we discussed the Hybrid Memory Cube Consurtium (HMC) milestone by one of the founding partners, Micron, of releasing 2GB HMC samples to the engineering community. The full production oriented samples utilize TSV technology to realize the high bandwidth memory interface for high performance computing environments. The technology will support up to 160GB/sec over 4 interface links to break the historic CPU to DRAM memory bandwith limits in traditional DDR interfaces.
The inital samples are being targeted to high end applications that will stress the bandwidth limits of the memory interface. This includes high performance computing at the workstation level, test equipment applications and DPI (deep packet inspection) packet buffers in the network space. The intent is to then push down intot he mid-range and compute oriented server space. There needs to be additional abstraction and some code re-architecting to maximize the advantages of the technology for lower end server markets. Micron’s HMC sample production features a 2GB memory cube that is composed of a stack of four 4Gb DRAM die.
HMC stacking technology
The Hybrid Memory Cube Consortium released it first specification (HMC1.0) a while back. The new product is based on this specification. Currently there is a version 2.0 in progress with a 1st haft 2014 target approval date. The V2.0 spec is targeting performance in power and bandwidth as improvement point over the initial release products. With the high performance of the memory, the issue for mission critical and financial applications is ECC and its impact on performance.
The ECC was clarified by an HMC spokesman from Micron as “DDR systems use the same ECC bits to cover the CPU memory channel all the way into the DRAM DIMMs and memory component arrays. HMC disconnects the two, the high speed links have their own CRC protection which is independent from the internal memory ECC managed by the vault controllers. For ECC to be effective in the memory arrays it is dependent on the physical structure of the memory stack (i.e. where banks are located either vertically or planer for a given memory access) which can be vendor dependent. Having the architecture setup like this helps customers identify where errors in their system and memory are actually happening (either in physical links with CRC vs. errors in the memory array with ECC). Today’s DDR systems they just see a ECC error and don’t know if it was due to the CPU, motherboard, DIMM, or actual memory component.
The initial parts are already working in several FPGA based systems and are spec’d for the commercial temperature range and environmentals. One of the target markets is the 100G networking applications that are seeking a memory solution fo the 4x25G systems that are challenged to find a DDR based memory interface for that speed. Higher density HMC products are needed to address this 100G marketplace. Micron expects their 4GB HMC engineering samples to be available in early 2014 with volume production of both the 2GB and 4GB HMC devices beginning later in 2014.